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authorMarcel Ziswiler <[email protected]>2018-08-31 18:37:47 +0200
committerThierry Reding <[email protected]>2018-09-26 16:45:41 +0200
commit7890d7856a989a7f2a4c46ec84c4ecda6a760c11 (patch)
treee4b0c770cfa9fc0b6c5140e010203ba2fc26c1c4 /tools/perf/scripts/python
parent4f6b07a2787b97380dc278ce28bd4438817f7525 (diff)
ARM: tegra: apalis_t30: annotate/clean-up pcie controller/port nodes
Annotate PCIe port nodes and clean-up PCIe controller/port status' with respect to carrier board vs. module level device trees. As port 3 connects to the on-module Gigabit Ethernet MACPHY it is always enabled together with the PCIe controller itself. Signed-off-by: Marcel Ziswiler <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
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