clk: bcm2835: Fix setting of PLL divider clock rates

Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write.  It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.

Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).

Cc: [email protected]
Signed-off-by: Eric Anholt <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

0 files changed, 0 insertions, 0 deletions