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authorKrzysztof Kozlowski <[email protected]>2022-05-05 13:38:02 +0200
committerBjorn Andersson <[email protected]>2022-07-02 21:50:11 -0500
commit74b0fbd6048f8f4caaed712ceeca52c6034e9ad6 (patch)
tree033ab94722170eab465545b4404046ae5827a12a /tools/perf/scripts/python
parentb2eab35be13d4537eb9f0e23846f2ab400bf63dd (diff)
arm64: dts: qcom: sdm630: correct QFPROM byte offsets
The NVMEM bindings expect that 'bits' property holds offset and size of region within a byte, so it applies a constraint of <0, 7> for the offset. Using 25 as HSTX trim offset is within 4-byte QFPROM word, but outside of the byte: sdm630-sony-xperia-nile-discovery.dtb: qfprom@780000: hstx-trim@240:bits:0:0: 25 is greater than the maximum of 7 sdm630-sony-xperia-nile-discovery.dtb: qfprom@780000: gpu-speed-bin@41a0:bits:0:0: 21 is greater than the maximum of 7 Align the offsets to match the bindings. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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