i2c: designware: make SCL and SDA falling time configurable

This patch allows to set independantly SCL and SDA falling times.
The tLOW period is computed by taking into account the SCL falling time.
The tHIGH period is computed by taking into account the SDA falling time.

For instance in case the margin on tLOW is considered too small, it can
be increased by increasing the SCL falling time which is by default set
at 300ns.

The same applies for tHIGH period with the help of SDA falling time.

Signed-off-by: Romain Baeriswyl <[email protected]>
Reviewed-by: Christian Ruppert <[email protected]>
Acked-by: Shinya Kuribayashi <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>

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