diff options
| author | Jernej Skrabec <[email protected]> | 2021-01-06 19:19:01 +0100 |
|---|---|---|
| committer | Maxime Ripard <[email protected]> | 2021-01-07 10:39:37 +0100 |
| commit | 62de535663e8bf4a5442bb11de7e4926a00eb93c (patch) | |
| tree | 9788a16c96935a12d69fbc15f30f651659290b25 /tools/perf/scripts/python | |
| parent | 3069a84fd67b05a3125e80cd7e2f7ea516421137 (diff) | |
ARM: dts: sun8i: r40: Add deinterlace node
R40 contains deinterlace core compatible to that in H3. One peculiarity
is that RAM gate is shared with CSI1. User manual states it's separate
but that's not true. Shared gate was verified with BSP Linux code check
and with runtime tests (CPU crashed if CSI1 gate was not ungated).
Signed-off-by: Jernej Skrabec <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python')
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