diff options
| author | Chen-Yu Tsai <[email protected]> | 2015-01-17 13:19:26 +0800 |
|---|---|---|
| committer | Maxime Ripard <[email protected]> | 2015-01-19 22:48:55 +0100 |
| commit | 61af4d8dceeb179b62cb342f4008ce3774d3d1fd (patch) | |
| tree | c5844e797e4e22ebf7472fa0d314960290eda6db /tools/perf/scripts/python | |
| parent | eb378df79e80772c1cbed32882b7378eb6f6c52c (diff) | |
clk: sunxi: Add mod0 and mmc module clock support for A80
The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.
As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.
This patch adds support for both.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions