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authorVille Syrjälä <[email protected]>2014-10-16 21:27:34 +0300
committerDaniel Vetter <[email protected]>2014-11-04 23:22:01 +0100
commit61234fa5e5232c35f87d44d9d596af4b10eac255 (patch)
treea63664a71dcba97d57a0604dadd381c21493b9a6 /tools/perf/scripts/python
parent093e3f134e2eff13503f708b81aecc2501e7aecb (diff)
drm/i915: Wait for PHY port ready before link training on VLV/CHV
There's no point in checking if the data lanes came out of reset after link training. If the data lanes aren't ready link training will fail anyway. Suggested-by: Todd Previte <[email protected]> Cc: Todd Previte <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Imre Deak <[email protected]> Acked-by: Todd Previte <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
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