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authorWu Hao <[email protected]>2018-06-30 08:53:15 +0800
committerGreg Kroah-Hartman <[email protected]>2018-07-15 13:55:45 +0200
commit5d56e117001996766c3dab5767663b0c43b76639 (patch)
tree90ca25fdad1af397732654f312f633ed8655fd33 /tools/perf/scripts/python
parentb16c5147dc3b1a03405f58f6864b56f29ab7aaf9 (diff)
fpga: dfl: add dfl_fpga_cdev_find_port
For feature devices, we need a method to find the port dedicated to the device. This patch adds a function dfl_fpga_cdev_find_port for this purpose. e.g. FPGA Management Engine (FME) Partial Reconfiguration sub feature, it uses this function to find dedicated port on the device for PR function implementation. Signed-off-by: Tim Whisonant <[email protected]> Signed-off-by: Enno Luebbers <[email protected]> Signed-off-by: Shiva Rao <[email protected]> Signed-off-by: Christopher Rauer <[email protected]> Signed-off-by: Xiao Guangrong <[email protected]> Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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