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| author | Rick Altherr <[email protected]> | 2017-03-28 14:52:59 -0700 |
|---|---|---|
| committer | Jonathan Cameron <[email protected]> | 2017-04-01 11:53:20 +0100 |
| commit | 573803234e72d182ec39692770110e574cd5b222 (patch) | |
| tree | 9c4dfe0ff91e55844e8d48f5ff605b33149ae793 /tools/perf/scripts/python | |
| parent | fb87ecf19e350d73206c5fbf28a28588f171f15d (diff) | |
iio: Aspeed ADC
Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
interrupts are supported by the hardware but are not currently implemented.
Signed-off-by: Rick Altherr <[email protected]>
Tested-by: Xo Wang <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions