diff options
| author | Wesley Chalmers <Wesley.Chalmers@amd.com> | 2022-11-03 22:29:31 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-03-15 18:18:00 -0400 |
| commit | 56574f89dbd84004c3fd6485bcaafb5aa9b8be14 (patch) | |
| tree | 92e29e6f259ad4cadca20880f88decef12ec78e0 /tools/perf/scripts/python | |
| parent | 709671ffb15dcd1b4f6afe2a9d8c67c7c4ead4a1 (diff) | |
drm/amd/display: Do not set DRR on pipe Commit
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
Cc: stable@vger.kernel.org
Cc: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions