diff options
| author | Wojciech Dubowik <[email protected]> | 2018-02-20 15:42:00 +0100 |
|---|---|---|
| committer | Kalle Valo <[email protected]> | 2018-02-27 18:47:29 +0200 |
| commit | 52c528ffaf1d4697e35c433a6a2ff81c469c967a (patch) | |
| tree | 6a0a15e71e80b049b17f923ae17bb70226888af3 /tools/perf/scripts/python | |
| parent | 91f1ee65d999a36241cb43bc820b1b59050bc79e (diff) | |
ath9k: Fix ack SIFS time for quarter/half channels
Ack timing generation has to be adapted for 5/10 MHz channels.
Do it by properly initializing ack shift field in TXSIFS
register. Ack shift assumes channel width of 2.5 Mhz so
value zero means 2.5 MHz, 1 is 5 MHz and so on.
Signed-off-by: Wojciech Dubowik <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions