diff options
| author | Sakari Ailus <[email protected]> | 2020-06-23 13:40:32 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2020-12-07 15:56:17 +0100 |
| commit | 4e1e8d240dff96bd8dd2c00c5fcd7f04088ace3c (patch) | |
| tree | b5738c25e951292d6dd82a158af6d0ef54f73a88 /tools/perf/scripts/python | |
| parent | ae502e08f45e47460406ab5c5fd2167a1011499a (diff) | |
media: ccs-pll: Add support for extended input PLL clock divider
CCS allows odd PLL dividers other than 1, granted that the corresponding
capability bit is set. Support this both in the PLL calculator and the CCS
driver.
Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions