aboutsummaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python
diff options
context:
space:
mode:
authorPaulo Zanoni <[email protected]>2013-12-19 19:12:31 -0200
committerDaniel Vetter <[email protected]>2014-02-12 18:53:07 +0100
commit3fddd40739de9c08099d1d488d24c42e0c210d6b (patch)
tree372355d61b7e882b7c666ac1eed32f9f14ef206c /tools/perf/scripts/python
parentf1ff6965e7ae5b5312ebba280570545f05409244 (diff)
drm/i915: remove the vblank_wait hack from HSW+
When I forked haswell_crtc_enable I copied all the code from ironlake_crtc_enable. The last piece of the function contains a big comment with a call to intel_wait_for_vblank. After this fork, we rearranged the Haswell code so that it enables the planes as the very last step of the modeset sequence, so we're sure that we call intel_enable_primary_plane after the pipe is really running, so the vblank waiting functions work as expected. I really believe this is what fixes the problem described by the big comment, so let's give it a try and get rid of that intel_wait_for_vblank, saving around 16ms per modeset (and init/resume). We can always revert if needed :) Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Jesse Barnes <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions