diff options
| author | Nicolas Pitre <[email protected]> | 2007-10-31 15:31:48 -0400 |
|---|---|---|
| committer | Russell King <[email protected]> | 2008-01-26 15:03:40 +0000 |
| commit | 3ebb5a2b44b02bddd5fbf0f29d71f1df6146c2c3 (patch) | |
| tree | 04d6e0c54c2bbd502f15044801c29157671d7568 /tools/perf/scripts/python | |
| parent | 15754bf98ff564e8bb5296c7f5e67bc59b5700aa (diff) | |
[ARM] add Feroceon support to compressed/head.S
The cache replacement policy on the Feroceon core doesn't guarantee
that reading through a linear chunk of memory flushes the entire cache.
This is however what the default method for ARMv5TE cores does.
Although the Feroceon is an ARMv5TE core, it implements the same
cache handling instructions as the ARMv5TEJ cores, and must use it for
proper cache flush.
Signed-off-by: Nicolas Pitre <[email protected]>
Acked-by: Russell King <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions