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| author | Clément Léger <clement.leger@bootlin.com> | 2022-06-06 16:57:01 +0200 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-07-20 11:05:48 +0300 |
| commit | 3b5a7ca7d252b96e9623b262414713828b2bd68f (patch) | |
| tree | eed183f9bcc26fb67a08bc5c992fac86aec8dca7 /tools/perf/scripts/python | |
| parent | c71572aa544ca64cbd2ff2052c79bc7e3573baed (diff) | |
ARM: at91: setup outer cache .write_sec() callback if needed
When running under OP-TEE, the L2 cache is configured by OP-TEE and the
sam platform code does not allow any modification yet. Setup a dummy
.write_sec() callback to avoid triggering exceptions when Linux tries
to modify the L2 cache configuration.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
[claudiu.beznea: keep .init_early populated only for SAMA5D2, remove
sam_secure_init() from sama5d2_init() as it is also called in
sama5_secure_cache_init()]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220606145701.185552-3-clement.leger@bootlin.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions