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authorTomasz Figa <[email protected]>2013-10-15 19:41:18 +0200
committerTomasz Figa <[email protected]>2013-12-30 18:15:48 +0100
commit3818f11740bbf87ad76f4f502f6739c8d62e5c17 (patch)
tree19cc5c3a76f11607db73d0bf500ea4da0f788de9 /tools/perf/scripts/python
parent796d1f4cd62500ee55a645f2649b546710b11bd1 (diff)
clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC documentation is the correct parent of DISP1 gate clocks. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Tested-by: Tomasz Figa <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
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