i2c: davinci: Optimize clock generation on Keystone SoC

According to "KeyStone Architecture Inter-IC Control Bus User Guide", fixed
additive part of frequency divisors (referred as "d" in the code and datasheet)
always equals to 6, independent of module clock prescaler.

                         module clock frequency
master clock frequency = ----------------------
                         (ICCL + 6) + (ICCH + 6)

It was not the case with original Davinci IP. Introduce new compatible property
"ti,keystone-i2c", which triggers special handling in the driver.

Without this change Keystone-based systems (having 204.8MHz input clock) choose
prescaler 29 (PSC=28). Using d=5 in this case leads to bus bitrate ~353kHz
instead of requested 400kHz. After correction, assuming d=6 bus rate is ~392kHz.
This gives ~11% transfer rate increase.

Signed-off-by: Alexander Sverdlin <[email protected]>
Reviewed-by: Grygorii Strashko <[email protected]>
Tested-by: Hemanth Guruva Reddy <[email protected]>
Tested-by: Lukasz Gemborowski <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>

0 files changed, 0 insertions, 0 deletions