diff options
| author | Peter De Schrijver <[email protected]> | 2017-02-23 12:44:39 +0200 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2017-03-20 14:04:45 +0100 |
| commit | 34ac2c278b306cc3006dd5cbfaff4ec52065bf6f (patch) | |
| tree | 1cac5e108c4f0c050fa796ed682777126beab16c /tools/perf/scripts/python | |
| parent | 9326947f2215e1816a9133b0b47e4c9200552777 (diff) | |
clk: tegra: Fix ISP clock modelling
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model
this as 1 mux/divider clock and child gate clocks.
Signed-off-by: Peter De Schrijver <[email protected]>
Reviewed-by: Mikko Perttunen <[email protected]>
Tested-by: Mikko Perttunen <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions