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authorSameer Pujar <[email protected]>2021-09-15 21:37:05 +0530
committerVinod Koul <[email protected]>2021-10-18 09:32:15 +0530
commit32de4745e20a639376735f198cccd0477f9aa396 (patch)
tree8066603d08080ef2c47706076b43bb3efe76a74e /tools/perf/scripts/python
parentc7f9c67ffb7be8aeafae7a4faee6738ac38a64bb (diff)
dmaengine: tegra210-adma: Override ADMA FIFO size
ADMAIF FIFO uses a ring buffer and it is divided amongst the available channels. The default FIFO size (in multiples of 16 words) of ADMAIF TX/RX channels is as below: * On Tegra210, channel 1 to 2 : size = 3 channel 3 to 10: size = 2 * On Tegra186 and later, channel 1 to 4 : size = 3 channel 5 to 20: size = 2 As per recommendation from HW, FIFO size of ADMA channel should be same as the corresponding ADMAIF channel it maps to. FIFO corruption is observed if the sizes do not match. We are using the default FIFO sizes for ADMAIF and there is no plan to support any custom values. Thus at runtime, override the ADMA channel FIFO size value depending on the corresponding ADMAIF channel. Signed-off-by: Sameer Pujar <[email protected]> Reviewed-by: Jon Hunter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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