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| author | Liu Yi L <yi.l.liu@intel.com> | 2020-07-24 09:49:17 +0800 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2020-07-24 10:51:21 +0200 |
| commit | 288d08e78008828416ffaa85ef274b4e29ef3dae (patch) | |
| tree | d6d0c95bbc0c5a64549268ffb2494ce28e5d14ba /tools/perf/scripts/python | |
| parent | e7e69461a83264dbce2b4ff480f858f3f1454db7 (diff) | |
iommu/vt-d: Handle non-page aligned address
Address information for device TLB invalidation comes from userspace
when device is directly assigned to a guest with vIOMMU support.
VT-d requires page aligned address. This patch checks and enforce
address to be page aligned, otherwise reserved bits can be set in the
invalidation descriptor. Unrecoverable fault will be reported due to
non-zero value in the reserved bits.
Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation cache types")
Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20200724014925.15523-5-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions