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authorAngeloGioacchino Del Regno <[email protected]>2021-01-14 18:47:16 +0100
committerVinod Koul <[email protected]>2021-01-19 20:36:01 +0530
commit26e6d50e93129af85a759820c1608be8b470f229 (patch)
tree7c09ca34025ac1dcc244a0ba14b9a525594b6565 /tools/perf/scripts/python
parentfcba632d8148ab3ec19f6c7dd015cca866357d7e (diff)
phy: qcom-qusb2: Allow specifying default clock scheme
The TCSR's PHY_CLK_SCHEME register is not available on all SoC models, but some may still use a differential reference clock. In preparation for these SoCs, add a se_clk_scheme_default configuration entry and declare it to true for all currently supported SoCs (retaining the previous defaults. This patch brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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