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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2019-03-07 22:53:19 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-04-02 10:31:05 +0200 |
| commit | 21ab095cbc069a351fa9cef919f2dafc43a8fde7 (patch) | |
| tree | 576eec4a8aacf56f1383d06154768ed6d3fcf293 /tools/perf/scripts/python | |
| parent | 3c14505c68ca6b3b4d5258886e238f2a81729f06 (diff) | |
clk: renesas: r8a77980: Fix RPC-IF module clock's parent
Testing has shown that the RPC-IF module clock's parent is the RPCD2
clock, not the RPC one -- the RPC-IF register reads stall otherwise...
Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions