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authorChanghwan Youn <[email protected]>2010-11-29 17:04:46 +0900
committerKukjin Kim <[email protected]>2010-12-08 18:11:37 +0900
commit1f2d6c49f087c84ed54ad3e0801faeca3e2ccfdd (patch)
tree3798b268d2d6bcd238483ee6a7e5cb91ae1a0b1a /tools/perf/scripts/python
parentb45756f65d90dca10cbe3e9ef04ecf96c01124a2 (diff)
ARM: S5PV310: Limit the irqs which support cascade interrupt
The irqs from SPI(0) to SPI(39) and SPI(51), SPI(53) are connected to the interrupt combiner. This patch limits the irqs which should be initialized to support cascade interrupt. Signed-off-by: Changhwan Youn <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
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