diff options
| author | Lucas Tanure <[email protected]> | 2021-05-25 10:08:19 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2021-05-25 16:45:03 +0100 |
| commit | 1c52825c38fc4e44c61ed75a8ae32f5fa580383b (patch) | |
| tree | afa3df527c85efca7aac5e4f53105ba59d48baf1 /tools/perf/scripts/python | |
| parent | d4e9889b02014a07c8dba3fbbae7205ea4084350 (diff) | |
ASoC: cs42l42: Fix 1536000 Bit Clock instability
The 16 Bits, 2 channels, 48K sample rate use case needs
to configure a safer pll_divout during the start of PLL
After 800us from the start of PLL the correct pll_divout
can be set
Signed-off-by: Lucas Tanure <[email protected]>
Reviewed-by: Richard Fitzgerald <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions