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authorChen-Yu Tsai <[email protected]>2019-12-15 17:59:14 +0100
committerMauro Carvalho Chehab <[email protected]>2020-01-04 08:17:57 +0100
commit1948dcf0f928b8bcdca57ca3fba8545ba380fc29 (patch)
tree642cd2b8f06675a284e0956b003395594da2c4a4 /tools/perf/scripts/python
parentcf9e6d5dbdd56ef2aa72f28c806711c4293c8848 (diff)
media: sun4i-csi: Fix [HV]sync polarity handling
The Allwinner camera sensor interface has a different definition of [HV]sync. While the timing diagram uses the names HSYNC and VSYNC, the note following the diagram and register names use HREF and VREF. Combined they imply the hardware uses either [HV]REF or inverted [HV]SYNC. There are also registers to set horizontal skip lengths in pixels and vertical skip lengths in lines, also known as back porches. Fix the polarity handling by using the opposite polarity flag for the checks. Also rename `[hv]sync_pol` to `[hv]ref_pol` to better match the hardware register description. Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver") Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Sakari Ailus <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
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