drm/amd/display: always use 4 dp lanes for dml

[why]
current DML logic uses currently trained setting for number
of dp lanes in DML calculations.  this is obviously flawed since
just because 1 lane is in use doesn't mean only 1 lane can be used

this causes mode validation to fail depending on current state,
which is incorrect

[how]
DML should always assume 4 lanes are available.  validation of
bandwidth is not supposed to be handled by DML, since we do
link validation without DML already

also, DML is expecting there to be a copy of the max state, this
state is removed when update_bounding_box is called to update
actual SKU clocks.  fix this as well by duping last state.

Signed-off-by: Jun Lei <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Acked-by: Eric Yang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

0 files changed, 0 insertions, 0 deletions