diff options
| author | Pramod Gurav <[email protected]> | 2015-09-30 15:26:58 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2015-10-04 19:15:17 +0100 |
| commit | 12b9b9f186f336ad6fe7adcbad48bd5340af9abb (patch) | |
| tree | 9f5d86b99cdf7516ae9b159e6d26ee9c4b1b1c5d /tools/perf/scripts/python | |
| parent | 2b0159d1ecfbc11badb96466c0c1582ee5ffe78f (diff) | |
tty: serial: msm: Add mask value for UART_DM registers
The bit masks for RFR_LEVEL1 and STALE_TIMEOUT_MSB values in MR1 and
IPR registers respectively are different for UART and UART_DM hardware
cores. We have been using UART core mask values for these. Add the same
for UART_DM core.
There is no bit setting as UART_IPR_RXSTALE_LAST for UART_DM core so do
it only for UART core.
Signed-off-by: Pramod Gurav <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Ivan T. Ivanov <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions