diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2018-07-09 17:16:00 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2018-08-30 08:38:26 -0500 |
| commit | 0ffc5df823dd3495441c47ea3ffaa09d4a57a5f1 (patch) | |
| tree | 69b2f5a5295dec4d8057f722e54874a8bd1eadd7 /tools/perf/scripts/python | |
| parent | 12b2982a1f72ce453d76da977e1dad422b2f34ad (diff) | |
ARM: dts: socfpga: update NAND clocking for c5/a5
The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). The
nand_x_clk and nand_ecc_clk are derived from the nand_clk. The nand_x_clk
has a fixed divider of 4.
Also, update the NAND dts property with the correct clocks property.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: add nand_ecc_clk and update commit message
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions