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authorPiyush Mehta <[email protected]>2021-09-13 19:30:05 +0530
committerGreg Kroah-Hartman <[email protected]>2021-10-10 15:05:24 +0200
commit05735f0854e1e2fc0dd266cc6f583fc79dfdd5d8 (patch)
treeeb906e732a436737a4f69b6922a3203fb09536e6 /tools/perf/scripts/python
parent2c52ad743fee10c0815db77a4e47f2416d407123 (diff)
usb: chipidea: udc: make controller hardware endpoint primed
Root-cause: There is an issue like endpoint is not recognized as primed, when bus have more pressure and the add dTD tripwire semaphore (ATDTW bit in USBCMD register) that can cause the controller to ignore a dTD that is added to a primed endpoint. This issue observed with the Windows10 host machine. Workaround: The software must implement a periodic cycle, and check for each dTD, if the endpoint is primed. It can do this by reading the corresponding bits in the ENDPTPRIME and ENDPTSTAT registers. If these bits are read at 0, the software needs to re-prime the endpoint by writing 1 to the corresponding bit in the ENDPTPRIME register. Added conditional revision check of 2.20[CI_REVISION_22]. Link: https://lore.kernel.org/linux-usb/SJ0PR02MB8644CBBA848A0F68323F1AA5D4D99@SJ0PR02MB8644.namprd02.prod.outlook.com/ Acked-by: Peter Chen <[email protected]> Signed-off-by: Piyush Mehta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
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