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authorManasi Navare <[email protected]>2018-10-23 12:12:48 -0700
committerManasi Navare <[email protected]>2018-10-31 16:22:08 -0700
commit03ad7d8821ec44513d514a5e6b17b60e732e1182 (patch)
tree4523039092ec8ba001a41b20b2c8af8cb968d71f /tools/perf/scripts/python
parentb4335ec0a3ee6229a570755f8fb95dc8a7c694f2 (diff)
drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
In case of Legacy DP connector on TypeC port, the flex IO DPMLE register is set to number of lanes configured by the display driver which will be programmed into DDI_BUF_CTL PORT_WIDTH_SELECTION. This needs to be programmed before enabling the shared PLLs hence add a pre_pll_enable hook for ICL and add this programming in that hook. v2: * Remove the check for combophy port (Jose) * Simplify the port reversal check logic (Jose) Cc: Lucas De Marchi <[email protected]> Cc: Jose Roberto de Souza <[email protected]> Cc: Animesh Manna <[email protected]> Cc: Paulo Zanoni <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Acked-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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