diff options
| author | Sam Protsenko <[email protected]> | 2024-01-19 19:29:46 -0600 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2024-01-24 15:11:43 +0000 |
| commit | 0229278bf33ea69cc1bba12c287f173e9b18c1f8 (patch) | |
| tree | 08c14984ef4de4cfe1c6bb427816ac620d01246d /tools/perf/scripts/python | |
| parent | 18ab9e9e8889ecba23a5e8b7f8924f09284e33d8 (diff) | |
spi: s3c64xx: Add Exynos850 support
Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which
can be configured in SPI mode:
* spi_0: BLK_PERI_SPI_0 (0x13940000)
* spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000)
* spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000)
SPI FIFO depth is 64 bytes for all those SPI blocks, so the
.fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the
default internal clock divider, and an internal loopback mode to run
a loopback test.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions