MIPS: tlbex: Avoid placing software PTE bits in Entry* PFN fields

Commit 748e787eb6de ("MIPS: Optimize TLB refill for RI/XI
configurations.") stopped explicitly clearing the bits used by software
in PTEs by making use of a rotate instruction that rotates them into the
fill bits of the Entry{Lo,Hi} register. This can only work if there are
actually enough fill bits in the register to cover the software
maintained bits, otherwise we end up writing those bits into the upper
bits of the PFN or PFNX field of the Entry{Lo,Hi} register.

Fix this by detecting the number of fill bits present in the
Entry{Lo,Hi} registers & explicitly clearing the software bits where
necessary.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Steven J. Hill <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Paul Gortmaker <[email protected]>
Cc: [email protected]
Cc: James Hogan <[email protected]>
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/11218/
Signed-off-by: Ralf Baechle <[email protected]>

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