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authorPeng Fan <peng.fan@nxp.com>2024-06-07 21:33:45 +0800
committerAbel Vesa <abel.vesa@linaro.org>2024-06-21 09:35:28 +0300
commite61352d5ecdc0da2e7253121c15d9a3e040f78a1 (patch)
treefe1b1b6bc8570d7635e6c7e8ff75c647d7ed9f02 /tools/perf/scripts/python/task-analyzer.py
parent236f32230c243b5f6f5e80730a8133fbded2beed (diff)
clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
The initialization order of SCU clocks affects the sequence of SCU clock resume. If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: 91e916771de0 ("clk: imx: scu: remove legacy scu clock binding support") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-14-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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