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| author | Siddharth Vadapalli <[email protected]> | 2024-02-04 14:33:36 +0530 |
|---|---|---|
| committer | Lee Jones <[email protected]> | 2024-02-23 14:58:02 +0000 |
| commit | cc1965b02d6cb18d9220dae06f7e2e0b0ebbea48 (patch) | |
| tree | 3e3998f74d66120757ef479c8a044c74796b35c8 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 9fb7369cf5dfcfff0dd0bae91c27d5d641d780e2 (diff) | |
dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible
The PCIE_CTRL registers within the CTRL_MMR space of TI's J784S4 SoC
are used to configure the link speed, lane count and mode of operation
of the respective PCIe instance. Add compatible for allowing the PCIe
driver to obtain a regmap for the PCIE_CTRL register within the System
Controller device-tree node in order to configure the PCIe instance
accordingly.
The Technical Reference Manual for J784S4 SoC with details of the
PCIE_CTRL registers is available at: https://www.ti.com/lit/zip/spruj52
Signed-off-by: Siddharth Vadapalli <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Lee Jones <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions