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author | Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> | 2024-04-12 11:37:06 -0700 |
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committer | Mathieu Poirier <mathieu.poirier@linaro.org> | 2024-04-16 10:26:22 -0600 |
commit | 9e1b2a0757d081e327630d566901c084b056d5fe (patch) | |
tree | 075924a1ebfc1f091943437af24031ca033646c3 /tools/perf/scripts/python/task-analyzer.py | |
parent | b31bcda55fcb3f282ffcb3047fcf760748b26a37 (diff) |
dt-bindings: remoteproc: Add Tightly Coupled Memory (TCM) bindings
Introduce bindings for TCM memory address space on AMD-xilinx Zynq
UltraScale+ platform. It will help in defining TCM in device-tree
and make it's access platform agnostic and data-driven.
Tightly-coupled memories(TCMs) are low-latency memory that provides
predictable instruction execution and predictable data load/store
timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory
banks on the ATCM and BTCM ports, for a total of 128 KB of memory.
The TCM resources(reg, reg-names and power-domain) are documented for
each TCM in the R5 node. The reg and reg-names are made as required
properties as we don't want to hardcode TCM addresses for future
platforms and for zu+ legacy implementation will ensure that the
old dts without reg/reg-names works and stable ABI is maintained.
It also extends the examples for TCM split and lockstep modes.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Link: https://lore.kernel.org/r/20240412183708.4036007-3-tanmay.shah@amd.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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