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authorKrzysztof Kozlowski <[email protected]>2023-03-08 19:33:17 +0100
committerBjorn Andersson <[email protected]>2023-03-21 20:40:03 -0700
commit6b2777fff8a9942cdcee82ae3f17d7f483a1e18c (patch)
tree6b53af56100435f082f1b03a82b8fd52923de845 /tools/perf/scripts/python/task-analyzer.py
parentf0d0966f87f9c38b74619bf7f0345f368af3a4c1 (diff)
arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config
Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec RESET_N reset pin. It also pulls the pin down in shutdown mode, thus it is more like a shutdown pin, not a reset. Use the same settings here for HDK8450 and keep the WCD9385 by default in powered off (so pin as low). Align the name of pin configuration node with other pins in the DTS. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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