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| author | Eric Chanudet <[email protected]> | 2024-08-05 13:42:51 -0400 |
|---|---|---|
| committer | Nishanth Menon <[email protected]> | 2024-08-28 12:15:50 -0500 |
| commit | 549833b697534a6f61840941b7c847669cfd77fa (patch) | |
| tree | b67d64b73e497402fbe8a9663b085477de901b96 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 1a314099b7559690fe23cdf3300dfff6e830ecb1 (diff) | |
arm64: dts: ti: k3-j784s4-main: Align watchdog clocks
assigned-clock sets DEV_RTIx_RTI_CLK(id:0) whereas clocks sets
DEV_RTIx_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT(id:1)[1]. This does not
look right, the timers in the driver assume a max frequency of 32kHz for
the heartbeat (HFOSC0 is 19.2MHz on j784s4-evm).
With this change, WDIOC_GETTIMELEFT return coherent time left
(DEFAULT_HEARTBEAT=60, reports 60s upon opening the cdev).
[1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html#clocks-for-rti0-device
Fixes: caae599de8c6 ("arm64: dts: ti: k3-j784s4-main: Add the main domain watchdog instances")
Suggested-by: Andrew Halaney <[email protected]>
Signed-off-by: Eric Chanudet <[email protected]>
Tested-by: Andrew Halaney <[email protected]>
Tested-by: Udit Kumar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions