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| author | Dmitry Baryshkov <[email protected]> | 2024-10-26 18:43:31 +0300 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2024-11-03 22:04:22 -0600 |
| commit | 53b3e2e0c9a36263be6874203c68bd7bd104663f (patch) | |
| tree | a1fbe8b983289835848f66a904ce061acada98af /tools/perf/scripts/python/task-analyzer.py | |
| parent | d088afa7de3cbe689954dad49e7058d2c4b8944c (diff) | |
dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P
Describe the last level cache controller on the SAR2130P and SAR1130P
platforms. They have 2 banks and also a separate register set to control
scratchpad slice.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
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