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| author | Alex Bee <[email protected]> | 2023-12-22 18:41:52 +0100 |
|---|---|---|
| committer | Rob Herring <[email protected]> | 2024-01-09 10:56:18 -0600 |
| commit | 4ec295efef1ac4969a9667b40e1e91fa45d90c4a (patch) | |
| tree | d0488e10d18f4bad349bcbe0c16ddc4fe3a858ac /tools/perf/scripts/python/task-analyzer.py | |
| parent | 76156d06769b20fed37d09b505808a74433b5e55 (diff) | |
dt-bindings: display: rockchip,inno-hdmi: Document RK3128 compatible
The integration for this SoC is different from the currently existing: It
needs it's PHY's reference clock rate to calculate the DDC bus frequency
correctly. The controller is also part of a powerdomain, so this gets added
as an mandatory property for this variant.
Signed-off-by: Alex Bee <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
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