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authorXianwei Zhao <[email protected]>2024-08-30 13:26:08 +0800
committerNeil Armstrong <[email protected]>2024-08-30 10:13:47 +0200
commit4ccba8cb2c5ca573d9bbf366e7d9d5e9761518c0 (patch)
treead2486ab576cce1a4872dee3068123521e7b0125 /tools/perf/scripts/python/task-analyzer.py
parentb2d7fd0ecb292e77a2d04cb6836c909cb6b6655b (diff)
dt-bindings: clock: fix C3 PLL input parameter
Add C3 PLL controller input clock parameters "fix". The clock named "fix" was initially implemented in PLL clock controller driver. However, some registers required secure zone access, so we moved it to the secure zone (BL31) and accessed it through SCMI. Since the PLL clock driver needs to use this clock, the "fix" clock is used as an input source. We updated the driver but forgot to modify the binding accordingly, so we are adding it here. It is an ABI break but on a new and immature platform. Noboby could really use that platform at this stage, so nothing is going to break on anyone really. Fixes: 0e6be855a96d ("dt-bindings: clock: add Amlogic C3 PLL clock controller") Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Xianwei Zhao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]>
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