diff options
| author | Lee Shawn C <[email protected]> | 2021-09-08 19:56:05 +0800 |
|---|---|---|
| committer | Vandita Kulkarni <[email protected]> | 2021-09-08 19:34:39 +0530 |
| commit | fe01883fdcefd09c7ceb91874c2f74ae074163d6 (patch) | |
| tree | fc3903591abb5731f1a3dcfdbbf495c21b83aade /tools/perf/scripts/python/syscall-counts.py | |
| parent | 5ebd50d3948ee596db02399a09b4561ed82aee57 (diff) | |
drm/i915: Get proper min cdclk if vDSC enabled
VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.
v2:
- Check for dsc enable and slice count ==1 then allow to
double confirm min cdclk value.
Cc: Ville Syrjala <[email protected]>
Cc: Jani Nikula <[email protected]>
Cc: Vandita Kulkarni <[email protected]>
Cc: Cooper Chiou <[email protected]>
Cc: William Tseng <[email protected]>
Signed-off-by: Lee Shawn C <[email protected]>
Reviewed-by: Vandita Kulkarni <[email protected]>
Acked-by: Jani Nikula <[email protected]>
Signed-off-by: Vandita Kulkarni <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions