diff options
| author | Anup Patel <apatel@ventanamicro.com> | 2022-01-18 11:12:40 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-04-21 17:45:39 +0530 |
| commit | d6f5f6e904be628941eeab7d6ae7d1fb9190c486 (patch) | |
| tree | 1e88572179a9b276fd30abbcce81765e8cf27f04 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 90deec51d726b4d829ca7a684595154bebdf8353 (diff) | |
RISC-V: Add AIA related CSR defines
The RISC-V AIA specification improves handling per-HART local interrupts
in a backward compatible manner. This patch adds defines for new RISC-V
AIA CSRs.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions