tty/8250_dw: Add support for OCTEON UARTS.

A few differences needed by OCTEON:

o These are DWC UARTS, but have USR at a different offset.

o Internal SoC buses require reading back from registers to maintain
  write ordering.

o 8250 on OCTEON appears with 64-bit wide registers, so when using
  readb/writeb in big endian mode we have to adjust the membase to hit
  the proper part of the register.

o No UCV register, so we hard code some properties.

Because OCTEON doesn't have a UCV register, I change where
dw8250_setup_port(), which reads the UCV, is called by pushing it in
to the OF and ACPI probe functions, and move unchanged
dw8250_setup_port() earlier in the file.

Signed-off-by: David Daney <[email protected]>
Acked-by: Greg Kroah-Hartman <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Heikki Krogerus <[email protected]>
Cc: [email protected]
Cc: Jamie Iles <[email protected]>
Cc: Jiri Slaby <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/5516/
Acked-by: Arnd Bergmann <[email protected]>
Reviewed-by: Heikki Krogerus <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>

0 files changed, 0 insertions, 0 deletions