diff options
| author | Zhenyu Wang <[email protected]> | 2010-11-02 17:30:46 +0800 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2010-11-02 10:05:46 +0000 |
| commit | d110852513148a7ec44fad4e036455aeb816d713 (patch) | |
| tree | 5c72fa12fa653804a4d13658a641a713d6849acd /tools/perf/scripts/python/syscall-counts.py | |
| parent | 328fc1325f144027f4a8269b11e9f8dcf1edcb97 (diff) | |
agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <[email protected]>
Signed-off-by: Chris Wilson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions