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authorRohit Khaire <[email protected]>2021-06-04 11:32:42 -0400
committerAlex Deucher <[email protected]>2021-06-04 16:02:50 -0400
commitcec7e80fbff58cdfd6595e7d11d7b2a38545c2e4 (patch)
tree99c984824bad17e40c44c621048b86b5eeae3fb2 /tools/perf/scripts/python/syscall-counts.py
parent18703923a66aecf6f7ded0e16d22eb412ddae72f (diff)
drm/amdgpu: Enable RLCG read/write interface for Sienna Cichlid
Enable this only for Sienna Cichild since only Navi12 and Sienna Cichlid support SRIOV Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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