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| author | Hien Huynh <[email protected]> | 2023-07-06 12:21:50 +0100 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2023-07-12 22:24:00 +0530 |
| commit | c6ec8c83a29fb3aec3efa6fabbf5344498f57c7f (patch) | |
| tree | 46f746a0119d0322193d07fe965098a0e3b7fc0c /tools/perf/scripts/python/syscall-counts.py | |
| parent | 7ab04b7cffa5aa646bfaf70d63634767dbf87eba (diff) | |
dmaengine: sh: rz-dmac: Fix destination and source data size setting
Before setting DDS and SDS values, we need to clear its value first
otherwise, we get incorrect results when we change/update the DMA bus
width several times due to the 'OR' expression.
Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC")
Cc: [email protected]
Signed-off-by: Hien Huynh <[email protected]>
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions