diff options
| author | Lucas Stach <[email protected]> | 2021-05-28 20:01:35 +0200 |
|---|---|---|
| committer | Abel Vesa <[email protected]> | 2021-06-14 17:05:45 +0300 |
| commit | c586f53ae159c6c1390f093a1ec94baef2df9f3a (patch) | |
| tree | cfe356547ba1ed04364fe4cefb1effd342ead8cf /tools/perf/scripts/python/syscall-counts.py | |
| parent | 18a50f82cd2ff3e43589d44349e71fdbef0d3fdd (diff) | |
clk: imx8mq: remove SYS PLL 1/2 clock gates
Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks
the uSDHC module which is sporadically unable to enumerate devices after
this change. Also it makes AMP clock management harder with no obvious
benefit to Linux, so just revert the change.
Link: https://lore.kernel.org/r/[email protected]
Fixes: b04383b6a558 ("clk: imx8mq: Define gates for pll1/2 fixed dividers")
Signed-off-by: Lucas Stach <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions