diff options
| author | Dinh Nguyen <[email protected]> | 2021-06-10 21:52:00 -0500 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2021-06-27 16:39:59 -0700 |
| commit | c2c9c5661a48bf2e67dcb4e989003144304acd6a (patch) | |
| tree | ecf6cd99a5031c2dcf5f48220f8f6ec70ca88542 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 6855ee839699bdabb4b16cf942557fd763bcb1fa (diff) | |
clk: agilex/stratix10: add support for the 2nd bypass
The EMAC clocks on Stratix10/Agilex/N5X have an additional bypass that
was not being accounted for. The bypass selects between
emaca_clk/emacb_clk and boot_clk.
Because the bypass register offset is different between Stratix10 and
Agilex/N5X, it's best to create a new function to calculate the bypass.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: [email protected]
Signed-off-by: Dinh Nguyen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions