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| author | Dnyaneshwar Bhadane <[email protected]> | 2023-10-24 15:07:37 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2023-12-21 11:43:19 -0500 |
| commit | bad3644dd8d5b118cdf64dfc71ef9540ee288ddc (patch) | |
| tree | 70a4485c0b53e92511a371f1568300235bb15ac8 /tools/perf/scripts/python/syscall-counts.py | |
| parent | c85d36be2993d65cfd678e01659ff69a4a803cad (diff) | |
drm/xe/xe2: Add initial workarounds
Add the initial collection of gt/engine/lrc workarounds.
While at it, add some newlines around the platform/IP comments to make
them consistent across all workarounds.
v2:
- FF_MODE is an MCR register (Matt Roper)
- Group 18032247524 with other Xe2 workarounds (Matt Roper)
- Move WA changing PSS_CHICKEN to lrc_was[] as for Xe2 that register
is part of the render context image (Matt Roper)
- Apply WA 16020518922 only on render engine (Matt Roper)
Signed-off-by: Dnyaneshwar Bhadane <[email protected]>
Signed-off-by: Shekhar Chauhan <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Lucas De Marchi <[email protected]>
Signed-off-by: Rodrigo Vivi <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions