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| author | Shawn Lin <[email protected]> | 2016-12-07 15:05:58 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2016-12-07 15:05:58 -0600 |
| commit | b8ab8e041cc0356323c1e4aee8047ea479650340 (patch) | |
| tree | ea3ee0e51fb9849440427e86196eb42d58738e4c /tools/perf/scripts/python/syscall-counts.py | |
| parent | 4816c4c7b82b55bb46cb9b85ef8e6780fc618592 (diff) | |
PCI: rockchip: Mark RC as common clock architecture
The default value of common clock configuration is zero indicating
Rockchip's RC is using asynchronous clock architecture but actually we are
using common clock. This will confuse some EP drivers if they need some
different settings referring to this value.
Set the Common Clock Configuration bit in the Link Control Register.
Signed-off-by: Shawn Lin <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions